The present invention relates to a non-volatile memory architecture. More specifically, the present invention relates to a symmetric non-volatile memory architecture that eliminates neighbor effect and does not require bit line pre-charge or pre-discharge.
FIG. 1 is a circuit diagram of a conventional non-volatile memory array 100. This array 100 includes non-volatile memory cells 101-114, select transistors 121-128, metal bit lines 131-134, diffusion bit lines 141-148, and word lines 151-152. As suggested by their names, metal bit lines 131-134 are formed by metal interconnect lines formed over a semiconductor substrate, and diffusion bit lines 141-148 are formed by conductively doped diffusion regions in the semiconductor substrate. The various elements of non-volatile memory array 100 are described in more detail in U.S. Pat. No. 5,963,465 by Eitan, entitled xe2x80x9cSymmetric Segmented Memory Array Architecturexe2x80x9d.
A critical parameter of non-volatile memory array 100 is the area that it occupies in the semiconductor substrate. Non-volatile memory array 100 is therefore designed to occupy a minimum area in the substrate. Additional rows of non-volatile memory transistors can be added to expand array 100 along the vertical axis. In addition, the structure of memory cells 101-104, 107-110, diffusion bit lines 141-144, select transistors 121-124 and metal bit lines 131-132, which is shown in dashed lines, can be repeated to expand array 100 along the horizontal axis.
The non-volatile memory transistors of array 100 are accessed through select transistors 121-128. For example, non-volatile memory transistor 102 is read as follows. Select signals SEL[1] and SEL[2] are asserted high, thereby turning on select transistors 122 and 123. As a result, metal bit line 131 is coupled to diffusion bit line 143, and metal bit line 132 is coupled to diffusion bit line 142. A source read voltage Vs is applied to diffusion bit line 143 through select transistor 122 and metal bit line 131. A drain read voltage Vd is applied to diffusion bit line 142 through select transistor 123 and metal bit line 132. Word line signal WL[0] is asserted high, thereby applying a logic high voltage to the gates of non-volatile memory transistors 101-107. Under these conditions, read current flows from metal bit line 132 to metal bit line 131 through transistor 102, with the magnitude of the read current depending on the threshold voltage of transistor 102. The read current is measured to provide information concerning the threshold voltage of transistor 102 (i.e., to determine whether transistor 102 is in a programmed or erased state).
During a read of non-volatile transistor 102, the current through transistor 102 is not protected from current that may flow to or from diffusion bit lines 141 and 144 through neighboring non-volatile transistors 101 and 103, respectively. This is referred to as xe2x80x9cneighbor effectxe2x80x9d.
For example, during a read of transistor 102, current can flow between diffusion bit lines 141 and 142 through neighbor transistor 101. Similarly, current can flow between diffusion bit lines 143 and 144 through neighbor transistor 103. The current flow through neighbor transistors 101 and 103 will depend on the threshold voltages of these transistors (i.e., whether these transistors 101 and 103 are programmed or erased). The measured read current of transistor 102 will be lower if a neighboring diffusion bit line is discharged, or higher if a neighboring diffusion bit line is charged. The neighbor effect can corrupt the read determination of the read transistor 102. Consequently, the diffusion bit lines of array 100 are typically pre-charged or pre-discharged prior to a read operation.
It would therefore be desirable to have a symmetric array that does not experience the neighbor effect, and does not require a pre-charge or pre-discharge operation.
Accordingly, the present invention provides a symmetric non-volatile memory array and method of operating that eliminates the neighbor effect, and does not require bit line pre-charge or pre-discharge.
More specifically, a method is provided for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to the source of a second non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first and second memory transistors, (2) applying a source voltage (Vs) to the source of the first memory transistor, (3) applying a drain voltage (Vd) to the drain of the first memory transistor and the source of the second memory transistor, and (4) applying a forcing voltage (Vf) to the drain of the second memory transistor.
In a particular embodiment, the drain voltage Vd is equal to the forcing voltage Vf. As a result, no read current will flow through the second memory transistor during a read of the first memory transistor. In addition, the source voltage Vs can be set to 0 Volts, such that another memory transistor, coupled to the source of the first transistor, will not disturb the read current through the first memory transistor. As a result, it is not necessary to pre-charge or pre-discharge bit lines of the array prior to a read operation.
In another embodiment, a non-volatile memory architecture is provided to allow the drain voltage Vd, the source voltage Vs and the forcing voltage Vf, to be applied to the non-volatile memory transistors in an array. In one embodiment, this array includes a first non-volatile memory transistor having a drain coupled to a first bit line, a second non-volatile memory transistor having a drain coupled to a second bit line and to the source of the first non-volatile memory transistor, and a third non-volatile memory transistor having a drain coupled to a third bit line and to the source of the second non-volatile memory transistor. In addition, means are provided to allow the forcing voltage Vf to be applied to the first bit line, the drain voltage Vd to be applied to the second bit line, and a second read voltage to be applied to the third bit line in order to perform a read operation of the second non-volatile memory transistor.
Each of the bit lines can include a diffusion bit line located in a semiconductor substrate, and a metal bit line located over the semiconductor substrate and coupled to the diffusion bit line. In one embodiment, a select transistor is coupled between each metal bit line and a corresponding diffusion bit line.
In another embodiment, a non-volatile memory architecture includes an array of non-volatile memory transistors arranged in rows and columns. A plurality of diffusion bit lines are provided, wherein each diffusion bit line is coupled to the drain of each transistor in one column of the array and the source of each transistor in an adjacent column of the array. A plurality of metal bit lines and a plurality of select transistors are also provided. Each metal bit line is coupled to a dedicated pair of select transistors, wherein one of the select transistors is coupled to one of the diffusion bit lines, and the other select transistor is coupled to another one of the diffusion bit lines, wherein the diffusion bit lines are separated by two other diffusion bit lines. This spacing enables the forcing voltage Vf, the drain voltage Vd and the source voltage Vs to be applied in an efficient manner.
Another embodiment of the present invention provides a method for reading a first non-volatile memory transistor in an array of non-volatile memory transistors, wherein the first non-volatile memory transistor has a drain coupled to the source of a second non-volatile memory transistor, and a source coupled to the drain of a third non-volatile memory transistor. The method includes the steps of (1) applying a read voltage to the gates of the first, second and third memory transistors, (2) applying a source voltage (Vs) to the source of the first memory transistor and the drain of the third memory transistor, (3) applying a drain voltage (Vd) to the drain of the first memory transistor and the source of the second memory transistor, (4) applying a first forcing voltage (Vf) to the drain of the second memory transistor; and (5) applying a second forcing voltage (Vfs) to the source of the third memory transistor.
The present invention will be more fully understood in view of the description and drawings provided below.